1 idt74fct16501at/ct fast cmos 18-bit registered transceiver industrial temperature range september 2009 idt74fct16501at/ct industrial temperature range fast cmos 18-bit registered transceiver description: the fct16501t 18-bit registered transceivers are built using advanced dual metal cmos technology. these high-speed, low-power 18-bit registered bus transceivers combine d-type latches and d-type flip-flops to allow data flow in transparent, latched and clocked modes. data flow in each direction is controlled by output-enable (oeab and oeba ), latch enable (leab and leba) and clock (clkab and clkba) inputs. for a-to-b data flow, the device operates in transparent mode when leab is high. when leab is low, the a data is latched if clkab is held at a high or low logic level. if leab is low, the a bus data is stored in the latch/flip-flop on the low-to-high transition of clkab. oeab is the output enable for the b port. data flow from the b port to the a port is similar but requires using oeba , leba and clkba. flow-through organization of signal pins simplifies layout. all inputs are designed with hysteresis for improved noise margin. the fct16501t are ideally suited for driving high-capacitance loads and low-impedance backplanes. the output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. oeba clkba leba oeab clkab leab b 1 a 1 c c d d d c d c to 17 other channels 1 30 28 27 55 2 3 54 features: ? 0.5 micron cmos technology ? high-speed, low-power cmos replacement for abt functions ? typical t sk(o) (output skew) < 250ps ? low input and output leakage 1a (max.) ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ? high drive outputs (?32ma i oh , 64ma i ol ) ? power off disable outputs permit ?live insertion? ? typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25c ? available in tssop package functional block diagram the idt logo is a registered trademark of integrated device technology, inc. ? 2009 integrated device technology, inc. dsc-5435/5
2 industrial temperature range idt74fct16501at/ct fast cmos 18-bit registered transceiver tssop top view pin configuration gnd b 2 b 3 gnd b 4 b 5 v cc b 6 b 7 b 1 b 8 b 9 b 10 b 11 gnd b 12 b 13 v cc b 14 gnd clkab b 16 b 15 b 17 gnd b 18 clkba gnd oeab leab a 1 gnd a 2 a 3 v cc a 4 a 5 gnd a 6 a 7 a 8 a 9 gnd a 10 a 11 v cc a 12 a 18 a 14 a 13 a 16 gnd a 17 leba a 15 oeba 47 37 38 39 40 41 42 43 44 45 46 33 34 35 36 56 55 49 50 51 52 53 54 48 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 29 30 31 32 25 26 27 28 pin names description oeab a-to-b output enable input oeba b-to-a output enable input (active low) leab a-to-b latch enable input leba b-to-a latch enable input clkab a-to-b clock input clkba b-to-a clock input a x a-to-b data inputs or b-to-a 3-state outputs b x b-to-a data inputs or a-to-b 3-state outputs pin description symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to 7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all device terminals except fct162xxx output and i/o terminals. 3. output and i/o terminals for fct162xxx. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6 pf c out output capacitance v out = 0v 3.5 8 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. inputs outputs oeab leab clkab ax bx lxxx z hhxl l hhxh h hl ll hl hh hllx b (2) hlhx b (3) function table (1, 4) notes: 1. a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, and clkba. 2. output level before the indicated steady-state input conditions were established. 3. output level before the indicated steady-state input conditions were established, provided that clkab was high before leab went low. 4. h = high voltage level l = low voltage level x = don't care z = high-impedance = low-to-high transition
3 idt74fct16501at/ct fast cmos 18-bit registered transceiver industrial temperature range symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (input pins) (5) v cc = max. v i = v cc ??1a input high current (i/o pins) (5) ??1 i il input low current (input pins) (5) v i = gnd ? ? 1 input low current (i/o pins) (5) ??1 i ozh high impedance output current v cc = max. v o = 2.7v ? ? 1 a i ozl (3-state output pins) (5) v o = 0.5v ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max., v o = gnd (3) ?80 ?140 ?250 ma v h input hysteresis ? ? 100 ? mv i ccl quiescent power supply current v cc = max. ? 5 500 a i cch v in = gnd or v cc i ccz dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 10% notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. duration of the condition can not exceed one second. 5. this test limit for this parameter is 5a at t a = ?55c. symbol parameter test conditions (1) min. typ. (2) max. unit i o output drive current v cc = max., v o = 2.5v (3) ?50 ? ?180 ma v oh output high voltage v cc = min. i oh = ?3ma 2.5 3.5 ? v in = v ih or v il i oh = ?15ma 2.4 3.5 ? v i oh = ?32ma (4) 23? v ol output low voltage v cc = min. i ol = 64ma ? 0.2 0.55 v v in = v ih or v il i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v ? ? 1 a output drive characteristics
4 industrial temperature range idt74fct16501at/ct fast cmos 18-bit registered transceiver symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply v cc = max. ? 0.5 1.5 ma current ttl inputs high v in = 3.4v (3) i ccd dynamic power supply current (4) v cc = max., v in = v cc ? 75 120 a / outputs open v in = gnd mhz oeab = oeba = v cc or gnd one input toggling 50% duty cycle i c total power supply current (6) v cc = max., v in = v cc ? 0.8 1.7 ma outputs open v in = gnd f cp = 10mhz (clkab) 50% duty cycle oeab = oeba = v cc leab = gnd v in = 3.4v ? 1.3 3.2 one bit toggling vin = gnd fi = 5mhz 50% duty cycle v cc = max., v in = v cc ? 3.8 6.5 (5) outputs open v in = gnd f cp = 10mhz (clkab) 50% duty cycle oeab = oeba = v cc leab = gnd v in = 3.4v ? 8.5 20.8 (5) eighteen bits toggling v in = gnd fi = 2.5mhz 50% duty cycle power supply characteristics notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + i cc d h n t + i ccd (f cp n cp /2 + fini) i cc = quiescent current (i ccl , i cch and i ccz ) i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at f i
5 idt74fct16501at/ct fast cmos 18-bit registered transceiver industrial temperature range fct16501at fct16501ct symbol parameter condition (1) min. (2) max. min. (2) max. unit f max clkab or clkba frequency (3) c l = 50pf ? 150 ? 150 mhz t plh propagation delay r l = 500 1.5 5.1 1.5 4.3 ns t phl ax to bx or bx to ax t plh propagation delay 1.5 5.6 1.5 4.4 ns t phl leba to ax, leab to bx t plh propagation delay 1.5 5.6 1.5 4.4 ns t phl clkba to ax, clkab to bx t pzh output enable time 1.5 6 1.5 4.8 ns t pzl oeba to ax, oeab to bx t phz output disable time 1.5 5.6 1.5 5.2 ns t plz oeba to ax, oeab to bx t su set-up time, high or low 3 ? 2.4 ? ns ax to clkab, bx to clkba t h hold time, high or low 0 ? 0 ? ns ax to clkab, bx to clkba t su set-up time high or low clock low 3 ? 2 ? ns ax to leab, bx to leba clock high 1.5 ? 1.5 ? t h hold time, high or low 1.5 ? 0.5 ? ns ax to leab, bx to leba t w leab or leba pulse width high (3) 3?3?ns t w clkab or clkba pulse width high or low (3) 3?3?ns t sk(o) output skew (4) ? 0.5 ? 0.5 ns switching characteristics over operating range notes: 1. see test circuits and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not tested. 4. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design.
6 industrial temperature range idt74fct16501at/ct fast cmos 18-bit registered transceiver pulse generator r t d.u.t. v cc v in c l v out 50pf 500 500 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h preset clear clock enable etc. high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh test circuits and waveforms propagation delay test circuits for all outputs enable and disable times pulse width set-up, hold, and release times test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns.
7 idt74fct16501at/ct fast cmos 18-bit registered transceiver industrial temperature range ordering information xx temp. range xxxx device type xx package pag thin shrink small outline package - green 18-bit registered transceiver 74 40 c to +85 c 16 double-density, 5 volt, high drive fct xxx family 501at 501ct corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com datasheet document history 09/28/09 pg. 7 updated the ordering information by removing the "idt" notation and non rohs part.
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